ARM Cortex A9 - A.7 AXI interfaces

Signal Descriptions
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A.7 AXI interfaces
In Cortex-A9 designs there can be two AXI master ports. The following sections describe the
AXI interfaces:
• AXI Master0 signals data accesses
• AXI Master1 signals instruction accesses on page A-11.
A.7.1 AXI Master0 signals data accesses
The following sections describe the AXI Master0 interface signals used for data read and write
accesses:
• Write address channel signals for AXI Master0
• Write data channel signals on page A-9
• Write response channel signals on page A-10
• Read address channel signals for AXI Master0 on page A-10
• Read data channel signals on page A-11
• AXI Master0 Clock enable signals on page A-11.
Write address channel signals for AXI Master0
Table A-8 shows the AXI write address channel signals for AXI Master0.
Table A-8 Write address channel signals for AXI Master0
Name I/O
Source or
destination
Description
AWADDRM0[31:0] O AXI system devices Address.
AWBURSTM0[1:0] O Burst type = b01, INCR incrementing burst.
AWCACHEM0[3:0] O Cache type giving additional information about cacheable characteristics,
determined by the memory type and Outer cache policy for the memory region.
AWIDM0[1:0] O Request ID.