ARM Cortex A9 User Manual

Signal Descriptions
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Read data channel signals
Table A-12 shows the AXI read data channel signals for AXI Master0.
AXI Master0 Clock enable signals
This section describes the AXI Master0 clock enable signals. Table A-13 shows the AXI
Master0 clock enable signal.
A.7.2 AXI Master1 signals instruction accesses
The following sections describe the AXI Master1 interface signals, that are used for instruction
accesses:
• Read address channel signals for AXI Master1 on page A-12
• Read data channel signals on page A-13
• AXI Master1 Clock enable signals on page A-13.
Table A-12 Read data channel signals for AXI Master0
Name I/O Source or destination Description
RVALIDM0 I AXI system devices Read valid
RDATAM0[63:0] IRead data
RRESPM0[1:0] I Read response
RLASTM0 I Read last indication
RIDM0[1:0] IRead ID
RREADYM0 O Read ready
Table A-13 Clock enable signal for AXI Master0
Name I/O Source Description
ACLKENM0 I Clock controller Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of
the system clock.
See Clocking and resets on page 2-6.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design