ARM Cortex A9 User Manual

Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-11
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7.6 Data prefetching
This section describes:
• The PLD instruction
• Data prefetching.
7.6.1 The PLD instruction
The Cortex-A9 processor handles all
PLD instructions in a dedicated unit with dedicated
resources. This avoids using resources in the integer core or the Load Store Unit.
PLD instructions are always executed and cannot be dropped.
7.6.2 Data prefetching
The Cortex-A9 data cache implements an automatic data prefetch mechanism that monitors
cache accesses by the processor. You can activate it in software, using a CP15 Auxiliary Control
Register bit. See Auxiliary Control Register on page 4-27.
The data prefetcher:
• can monitor and prefetch up to eight independent data streams
• monitors cache line requests performed by the processor, cache misses, and starts after a
few iterations on a regular pattern, either ascending or descending, with a maximum stride
of 8 cache lines
• works on confirmation, and continues to prefetch and allocate the data in the L1 data
cache, as long as it keeps hitting in the prefetched cache line
• stops prefetching when:
— it crosses a 4kB page boundary
— it changes context
— a DSB or a PLD instruction executes
— the executing program does not hit in the prefetched cache lines.
Requests from PLD instructions always take precedence over requests from the data prefetch
mechanism.
Prefetched lines in the speculative prefetcher can be dropped before they are allocated.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design