ARM Cortex A9 User Manual

Signal Descriptions
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A.3 Interrupts
Table A-3 shows the interrupt line signals.
Table A-3 Interrupt line signals
Name I/O Source Description
nFIQ I Interrupt sources Cortex-A9 processor FIQ request input line.
Active-LOW fast interrupt request:
0 Activate fast interrupt.
1 Do not activate fast interrupt.
The processor treats the nFIQ input as level sensitive.
nIRQ I Interrupt sources Cortex-A9 processor IRQ request input line.
Active-LOW interrupt request:
0 Activate interrupt.
1 Do not activate interrupt.
The processor treats the nIRQ input as level sensitive.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design