ARM Cortex A9 User Manual

Cycle Timings and Interlock Behavior
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. B-9
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B.6 Serializing instructions
Out of order execution is not always possible. Some instructions are serializing. Serializing
instructions force the processor to complete all modifications to flags and general-purpose
registers by previous instructions before the next instruction is executed.
This section describes timings for serializing instructions.
B.6.1 Serializing instructions
The following exception entry instructions are serializing:
•
SVC
•
SMC
•
BKPT
• instructions that take the prefetch abort handler
• instructions that take the Undefined Instruction exception handler.
The following instructions that modify mode or program control are serializing:
•
MSR CPSR when they modify control or mode bits
• data processing to PC with the S bit set (for example,
MOVS pc, r14 )
•
LDM pc ^.
•
CPS
• SETEND
• RFE .
The following instructions are serializing:
•all
MCR to CP14 or CP15 except ISB and DMB
• MRC p14 for debug registers
•
WFE , WFI , SEV
• CLREX
• DSB .
In the r1p0 implementation
DMB waits for all previous LDR / STR instructions to finish, not for all
instructions to finish.
The following instruction, that modifies the SPSR, is serializing:
•
MSR SPSR .

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design