ARM Cortex A9 User Manual

Introduction
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-10
ID073015 Non-Confidential
1.8 Product documentation and design flow
This section describes the Cortex-A9 processor books, and how they relate to the design flow in:
• Documentation
• Design flow on page 1-11.
See Additional reading on page ix for more information about the books described in this
section. For information about the relevant architectural standards and protocols, see
Compliance on page 1-5.
1.8.1 Documentation
The Cortex-A9 documentation is as follows:
Technical Reference Manual
The Technical Reference Manual (TRM) describes the functionality and the
effects of functional options on the behavior of the Cortex-A9 family of
processors. It is required at all stages of the design flow. The choices made in the
design flow can mean that some behavior described in the TRM is not relevant.
The following TRMs are available with the Cortex-A9 deliverables:
• the Cortex-A9 TRM describes the uniprocessor variant.
• the Cortex-A9 MPCore TRM describes the multiprocessor variant of the
Cortex-A9 processor.
• the Cortex-A9 Floating-Point Unit (FPU) TRM describes the
implementation-specific FPU parts of the data engine.
• the Cortex-A9 NEON Media Processing Engine TRM describes the
Advanced SIMD Cortex-A9 implementation-specific parts of the data
engine.
If you are programming the Cortex-A9 processor then contact:
• the implementer to determine:
— the build configuration of the implementation
— what integration, if any, was performed before implementing the
Cortex-A9 processor.
• the integrator to determine the pin configuration of the device that you are
using.
Configuration and Sign-Off Guide
The Configuration and Sign-Off Guide (CSG) describes:
• the available build configuration options and related issues in selecting
them
• how to configure the Register Transfer Level (RTL) source files with the
build configuration options
• how to integrate RAM arrays
• how to run test vectors
• the processes to sign off the configured design.
The ARM product deliverables include reference scripts and information about
using them to implement your design. Reference methodology documentation
from your EDA tools vendor complements the CSG.
The CSG is a confidential book that is only available to licensees.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design