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Cycle Timings and Interlock Behavior

ID073015 Non-Confidential

B.1 About instruction cycle timing

This chapter provides information to estimate how much execution time particular code

sequences require. The complexity of the Cortex-A9 processor makes it impossible to calculate

precise timing information manually. The timing of an instruction is often affected by other

concurrent instructions, memory system activity, and additional events outside the instruction

flow. Detailed descriptions of all possible instruction interactions, and all possible events taking

place in the processor, is beyond the scope of this document.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design