ARM Cortex A9 User Manual

Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-15
ID073015 Non-Confidential
2.5 Constraints and limitations of use
This section describes memory consistency.
Memory coherency in a Cortex-A9 processor is maintained following a weakly ordered memory
consistency model.
Note
When the Shareable attribute is applied to a memory region that is not Write-Back, Normal
memory, data held in this region is treated as Non-cacheable.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design