Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-15
ID073015 Non-Confidential
2.5 Constraints and limitations of use
This section describes memory consistency.
Memory coherency in a Cortex-A9 processor is maintained following a weakly ordered memory
consistency model.
When the Shareable attribute is applied to a memory region that is not Write-Back, Normal
memory, data held in this region is treated as Non-cacheable.
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