ARM Cortex A9 User Manual

Jazelle DBX registers
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5.3 CP14 Jazelle register descriptions
The following sections describe the CP14 Jazelle DBX registers arranged in numerical order, as
shown in Table 5-1 on page 5-3:
• Jazelle ID Register
• Jazelle Operating System Control Register on page 5-5
• Jazelle Main Configuration Register on page 5-6
• Jazelle Parameters Register on page 5-7
• Jazelle Configurable Opcode Translation Table Register on page 5-8.
5.3.1 Jazelle ID Register
The JIDR characteristics are:
Purpose Enables software to determine the implementation of the Jazelle Extension
provided by the processor.
Usage constraints The JIDR is:
• accessible in privileged modes.
• also accessible in User mode if the CD bit is clear. See Jazelle
Operating System Control Register on page 5-5.
Configurations Available in all configurations.
Attributes See the register summary in Table 5-1 on page 5-3.
Figure 5-1 shows the JIDR bit assignments.
Figure 5-1 JIDR bit assignments
Table 5-2 shows the JIDR bit assignments.
To access the JIDR, read the CP14 register with:
MRC p14, 7, <Rd>, c0, c0, 0; Read Jazelle Identity Register
31 28 27 20 12 11 8 7 6 5 0
Arch Design SArchMajor SArchMinor
RAZ
TrTableSz
TrTbleFrm
Table 5-2 JIDR bit assignments
Bits Name Function
[31:28] Arch This uses the same architecture code that appears in the Main ID register.
[27:20] Design Contains the implementer code of the designer of the subarchitecture.
[19:12] SArchMajor The subarchitecture code.
[11:8] SArchMinor The subarchitecture minor code.
[7] - RAZ.
[6] TrTbleFrm Indicates the format of the Jazelle Configurable Opcode Translation Table Register.
[5:0] TrTbleSz Indicates the size of the Jazelle Configurable Opcode Translation Table Register.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design