ARM Cortex A9 User Manual

Jazelle DBX registers
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Table 5-5 shows the Jazelle Parameters Register bit assignments.
To access the Jazelle Parameters Register, read or write the CP14 register with:
MRC p14, 7, <Rd>, c3, c0, 0; Read Jazelle Parameters Register
MCR p14, 7, <Rd>, c3, c0, 0; Write Jazelle Parameters Register
5.3.5 Jazelle Configurable Opcode Translation Table Register
The Jazelle Configurable Opcode Translation Table Register characteristics are:
Purpose Provides translations between the configurable opcodes in the range
0xCB-0xFD and the operations that are provided by the Jazelle hardware.
Usage constraints Only accessible in privileged modes.
Configurations Available in all configurations.
Attributes See the register summary in Table 5-1 on page 5-3.
Figure 5-5 shows the Jazelle Configurable Opcode Translation Table Register bit assignments.
Figure 5-5 Jazelle Configurable Opcode Translation Table Register bit assignments
Table 5-6 shows the Jazelle Configurable Opcode Translation Table Register bit assignments.
Table 5-5 Jazelle Parameters Register bit assignments
Bits Name Function
[31:22] - UNK/SBZP.
[21:17] BSH The Bounds SHift (BSH) bits contain the offset, in bits, of the array bounds (number of items in the array) within
the array descriptor word.
[16:12] sADO The signed Array Descriptor Offset (sADO) bits contain the offset, in words, of the array descriptor word from an
array reference. The offset is a sign-magnitude signed quantity:
• Bit [16] gives the sign of the offset. The offset is positive if the bit is clear, and negative if the bit is set.
• Bits [15:12] give the absolute magnitude of the offset.
[11:8] ARO The Array Reference Offset (ARO) bits contain the offset, in words, of the array data or the array data pointer from
an array reference.
[7:4] STO The STatic Offset (STO) bits contain the offset, in words, of the static or static pointer from a static reference.
[3:0] ODO The Object Descriptor Offset (ODO) bits contain the offset, in words, of the field from the base of an object data
block.
31 16 15 10 9 4 3 0
UNK/SBZP Opcode UNK/SBZP Operation
Table 5-6 Jazelle Configurable Opcode Translation Table Register bit assignments
Bits Name Function
[31:16] - UNK/SBZP

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design