ARM Cortex A9 User Manual

Jazelle DBX registers
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 5-9
ID073015 Non-Confidential
To access the Jazelle Configurable Opcode Translation Table Register, write the CP14 register
with:
MCR p14, 7, <Rd>, c4, c0, 0; Write Jazelle Configurable Opcode Translation
Table Register
[15:10] Opcode Contains the bottom bits of the configurable opcode
[9:4] - UNK/SBZP
[3:0] Operation Contains the code for the operation 0x0 - 0x9
Table 5-6 Jazelle Configurable Opcode Translation Table Register bit assignments
Bits Name Function

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design