Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-2
ID073015 Non-Confidential
7.1 About the L1 memory system
The L1 memory system has:
• separate instruction and data caches each with a fixed line length of 32 bytes
• 64-bit data paths throughout the memory system
• support for four sizes of memory page
• export of memory attributes for external memory systems
• support for Security Extensions.
The data side of the L1 memory system has:
• two 32-byte linefill buffers and one 32-byte eviction buffer
• a 4-entry, 64-bit merging store buffer.
You must invalidate the instruction cache, the data cache, TLB, and BTAC before using them.
7.1.1 Memory system
This section describes:
• Cache features
• Instruction cache features
• Data cache features on page 7-3
• Store buffer on page 7-3.
Cache features
The Cortex-A9 processor has separate instruction and data caches. The caches have the
following features:
• Each cache can be disabled independently. See System Control Register on page 4-25.
• Both caches are 4-way set-associative.
• The cache line length is eight words.
• On a cache miss, critical word first filling of the cache is performed.
• You can configure the instruction and data caches independently during implementation
to sizes of 16KB, 32KB, or 64KB.
• To reduce power consumption, the number of full cache reads is reduced by taking
advantage of the sequential nature of many cache operations. If a cache read is sequential
to the previous cache read, and the read is within the same cache line, only the data RAM
set that was previously read is accessed.
Instruction cache features
The instruction cache has the following features:
• The instruction cache is virtually indexed and physically tagged.
• Instruction cache replacement policy is either pseudo round-robin or pseudo random.
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