ARM Cortex A9 User Manual

ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-1
ID073015 Non-Confidential
Chapter 7
Level 1 Memory System
This chapter describes the L1 Memory System. It contains the following sections:
• About the L1 memory system on page 7-2
• Security Extensions support on page 7-4
• About the L1 instruction side memory system on page 7-5
• About the L1 data side memory system on page 7-8
• About DSB on page 7-10
• Data prefetching on page 7-11
• Parity error support on page 7-12.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design