System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-3
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4.2 Register summary
This section gives a summary of the CP15 system control registers. For more information on
using the CP15 system control registers, see the ARM Architecture Reference Manual.
The system control coprocessor is a set of registers that you can write to and read from. Some
of these registers support more than one type of operation.
This section describes the CP15 system control registers grouped by CRn order, and accessed
by the
MCR
and
MRC
instructions in the order of CRn, Op1, CRm, Op2:
• c0 registers on page 4-5
• c1 registers on page 4-6
• c2 registers on page 4-6
• c3 registers on page 4-6
• c4 registers on page 4-7
• c5 registers on page 4-7
• c6 registers on page 4-7
• c7 registers on page 4-8
• c8 registers on page 4-9
• c9 registers on page 4-9
• c10 registers on page 4-10
• c11 registers on page 4-10
• c12 registers on page 4-10
• c13 registers on page 4-11
• c14 registers on page 4-11
• c15 registers on page 4-11.
All system control coprocessor registers are 32 bits wide, except for the Program New Channel
operation described in PLE Program New Channel operation on page 9-5. Reserved registers
are RAZ/WI.
In addition to listing the CP15 system control registers by CRn ordering, the following
subsections describe the CP15 system control registers by functional group:
• Identification Registers on page 4-12
• Virtual memory control registers on page 4-13
• Fault handling registers on page 4-13
• Other system control registers on page 4-13
• Cache maintenance operations on page 4-14
• Address translation operations on page 4-14
• Miscellaneous operations on page 4-15
• Performance monitor registers on page 4-15
• Security Extensions registers on page 4-16
• Preload Engine registers on page 4-16
• TLB maintenance on page 4-17
• Implementation defined registers on page 4-17.
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