ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-15
ID073015 Non-Confidential
4.2.23 Miscellaneous operations
Table 4-22 shows the 32-bit wide miscellaneous operations.
4.2.24 Performance monitor registers
Table 4-23 shows the 32-bit wide performance monitor registers.
Table 4-22 Miscellaneous system control operations
CRn Op1 CRm Op2 Name Type Reset Description
c1 0 c1 3 VCR RW
0x00000000 Virtualization Control Register on page 4-34
c7 0 c0 4
NOP
a
WO - -
c13 0 c0 2 TPIDRURW RW - Software Thread ID registers
3 TPIDRURO
RW
b
-
4 TPIDRPRW RW -
a. This operation is performed by the WFI instruction. See Deprecated registers on page 4-2.
b. RO in User mode.
Table 4-23 Performance monitor registers
CRn Op1 CRm Op2 Name Type Reset Description
c90c120PMCR RW
0x41093000 Performance Monitor Control Register
1PMCNTENSETRW
0x00000000 Count Enable Set Register
2PMCNTENCLRRW
0x00000000 Count Enable Clear Register
3 PMOVSR RW - Overflow Flag Status Register
4 PMSWINC WO - Software Increment Register
5 PMSELR RW
0x00000000 Event Counter Selection Register
c13 0 PMCCNTR RW - Cycle Count Register
1 PMXEVTYPER RW - Event Type Selection Register
2 PMXEVCNTR RW - Event Count Registers
c14 0 PMUSERENR
RW
a
0x00000000 User Enable Register
1PMINTENSETRW
0x00000000 Interrupt Enable Set Register
2PMINTENCLRRW
0x00000000 Interrupt Enable Clear Register
a. RO in User mode.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design