System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-34
ID073015 Non-Confidential
4.3.14 Virtualization Control Register
The VCR characteristics are:
Purpose Forces an exception regardless of the value of the A, I, or F bits in the
Current Program Status Register (CPSR).
Usage constraints The VCR is:
• only accessible in privileged modes
• only accessible in Secure state.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-3 on page 4-6.
Figure 4-13 shows the VCR bit assignments.
Figure 4-13 VCR bit assignments
Table 4-40 shows the VCR bit assignments.
To access the VCR, read or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c1, 3; Read VCR data
MCR p15, 0,<Rd>, c1, c1, 3; Write VCR data
31 0
UNK/SBZP
56789
UNK/SBZP
Abort Mask Override
IRQ Mask Override
FIQ Mask Override
Table 4-40 VCR bit assignments
Bits Name Function
[31:9] - UNK/SBZP.
[8] AMO Abort Mask Override.
When the processor is in Non-secure state and the SCR.EA bit is set, if the AMO bit is set, this enables an
asynchronous Data Abort exception to be taken regardless of the value of the CPSR.A bit.
When the processor is in Secure state, or when the SCR.EA bit is not set, the AMO bit is ignored.
[7] IMO IRQ Mask Override.
When the processor is in Non-secure state and the SCR.IRQ bit is set, if the IMO bit is set, this enables an IRQ
exception to be taken regardless of the value of the CPSR.I bit.
When the processor is in Secure state, or when the SCR.IRQ bit is not set, the IMO bit is ignored.
[6] IFO FIQ Mask Override.
When the processor is in Non-secure state and the SCR.FIQ bit is set, if the IFO bit is set, this enables an FIQ
exception to be taken regardless of the value of the CPSR.F bit.
When the processor is in Secure state, or when the SCR.FIQ bit is not set, the IFO bit is ignored.
[5:0] - UNK/SBZP.
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