ARM Cortex A9 User Manual

Signal Descriptions
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A.11 MBIST interface
Table A-21 shows the MBIST interface signals. These signals are present only when the BIST
interface is present.
The size of some MBIST signals depends on whether the implementation has parity support or
not. Table A-22 shows these signals with parity support implemented.
Table A-23 shows these signals without parity support implemented.
See the Cortex-A9 MBIST TRM for a description of MBIST.
Table A-21 MBIST interface signals
Name I/O Source Description
MBISTADDR[10:0] I MBIST controller MBIST address bus
MBISTARRAY[19:0] I MBIST arrays used for testing RAMs
MBISTENABLE IMBIST test enable
MBISTWRITEEN I Global write enable
MBISTREADEN I Global read enable
Table A-22 MBIST signals with parity support implemented
Name I/O Source or destination Description
MBISTBE[32:0] I MBIST controller MBIST write enable
MBISTINDATA[71:0] IMBIST data in
MBISTOUTDATA[71:0] O MBIST data out
Table A-23 MBIST signals without parity support implemented
Name I/O Source/Destination Description
MBISTBE[25:0] I MBIST controller MBIST write enable
MBISTINDATA[63:0] IMBIST data in
MBISTOUTDATA[63:0] O MBIST data out

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design