ARM Cortex A9 User Manual

System Control
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4.3.22 Power Control Register
The Power Control Register characteristics are:
Purpose Enables you to set:
• the clock latency for your implementation of the Cortex-A9
processor
• dynamic clock gating.
Usage constraints • a read/write register in Secure state
• a read-only register in Non-secure state.
Configurations Available in all configurations.
Attributes See the register summary in Table 4-15 on page 4-11.
Figure 4-21 shows the Power Control Register bit assignments.
Figure 4-21 Power Control Register bit assignments
Table 4-48 shows the Power Control Register bit assignments.
To access the Power Control Register, read or write the CP15 register with:
MRC p15,0,<Rd>,c15,c0,0; Read Power Control Register
MCR p15,0,<Rd>,c15,c0,0; Write Power Control Register
31 11 10 8 7 1 0
max_clock_latency
Enable dynamic clock gating
Reserved Reserved
Table 4-48 Power Control Register bit assignments
Bits Name Function
[31:11] - Reserved.
[10:8] max_clk_latency Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an implementation-specific parameter. ARM strongly recommends that the
software does not modify it.
The max_clk_latency bits determine the length of the delay between when one of these blocks has its
clock cut and the time when it can receive new active signals.
If the value determined by max_clk_latency is lower than the real delay, the block that had its clock
cut can receive active signals even though it does not have a clock. This can cause the device to
malfunction.
If the value determined by max_clk_latency is higher than the real delay, the master block waits extra
cycles before sending its signals to the block that had its clock cut. This can have some performance
impact.
When the value is correctly set, the block that had its clock cut receives active signals on the first clock
edge of the wake-up. This gives optimum performance.
[7:1] - Reserved.
[0] Enable dynamic
clock gating
Disabled at reset.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design