ARM Cortex A9 - 8.1 About the Cortex-A9 L2 interface

Level 2 Memory Interface
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8.1 About the Cortex-A9 L2 interface
This section describes the Cortex-A9 L2 interface in:
• Cortex-A9 L2 interface
• Supported AXI transfers on page 8-3
• AXI transaction IDs on page 8-3
• AXI USER bits on page 8-4.
• Exclusive L2 cache on page 8-5.
8.1.1 Cortex-A9 L2 interface
The Cortex-A9 L2 interface consists of two 64-bit wide AXI bus masters:
• M0 is the data side bus
• M1 is the instruction side bus and has no write channels.
Table 8-1 shows the AXI master 0 interface attributes.
Table 8-2 shows the AXI master 1 interface attributes.
Table 8-1 AXI master 0 interface attributes
Attribute Format
Write issuing capability 12, including:
• eight noncacheable writes
• four evictions.
Read issuing capability 10, including:
• six linefill reads.
• four noncacheable read
Combined issuing capability 22
Write ID capability 2
Write interleave capability 1
Write ID width 2
Read ID capability 3
Read ID width 2
Table 8-2 AXI master 1 interface attributes
Attribute Format
Write issuing capability None
Read issuing capability 4 instruction reads
Combined issuing capability 4
Write ID capability None
Write interleave capability None