ARM Cortex A9 User Manual

Level 2 Memory Interface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 8-4
ID073015 Non-Confidential
• For the instruction side read bus, ARIDM1, is encoded as follows:
— 2'b00 for outstanding transactions
— 2'b01 for outstanding transactions
— 2'b10 for outstanding transactions
— 2'b11 for outstanding transactions.
• For the data side write bus, AWI DM 0 , is encoded as follows:
— 2'b00 for noncacheable accesses
— 2'b01 is unused
— 2'b10 for linefill 0 evictions
— 2'b11 for linefill 1 evictions.
8.1.4 AXI USER bits
The AXI USER bits encodings are as follows:
Data side read bus, ARUSERM0[6:0]
Table 8-3 shows the bit encodings for ARUSERM0[6:0]
Instruction side read bus, ARUSERM1[6:0]
Table 8-4 shows the bit encodings for ARUSERM1[6:0].
Table 8-3 ARUSERM0[6:0] encodings
Bits Name Description
[6] Reserved b0
[5] L2 Prefetch hint Indicates that the read access is a prefetch hint to the L2, and does not expect any data back
[4:1] Inner attributes
b0000 Strongly Ordered
b0001 Device
b0011 Normal Memory Non-Cacheable
b0110 Write-Through
b0111 Write-Back no Write-Allocate
b1111 Write-Back Write-Allocate.
[0] Shared bit 0 Nonshared
1 Shared.
Table 8-4 ARUSERM1[6:0] encodings
Bits Name Description
[6] Reserved b0

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design