Level 2 Memory Interface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 8-3
ID073015 Non-Confidential
The numbers in Table 8-1 on page 8-2 and Table 8-2 on page 8-2 are the theoretical maximums
for the Cortex-A9 MPCore processor. A typical system is unlikely to reach these numbers. ARM
recommends that you perform profiling to tailor your system resources appropriately for
optimum performance.
The AXI protocol and meaning of each AXI signal are not described in this document. For more
information see AMBA AXI Protocol v1.0 Specification.
8.1.2 Supported AXI transfers
The Cortex-A9 master ports generate only a subset of all possible AXI transactions.
For cacheable transactions:
• WRAP4 64-bit for read transfers (linefills)
• INCR4 64-bit for write transfers (evictions)
For noncacheable transactions:
• INCR N (N:1- 9) 64-bit read transfers
• INCR 1 for 64-bit write transfers
• INCR N (N:1-16) 32-bit read transfers
• INCR N (N:1-2) for 32-bit write transfers
• INCR 1 for 8-bit and 16-bit read/write transfers
• INCR 1 for 8-bit, 16-bit, 32-bit, 64-bit exclusive read/write transfers
• INCR 1 for 8-bit and 32-bit read/write (locked) for swap
The following points apply to AXI transactions:
• WRAP bursts are only read transfers, 64-bit, 4 transfers
• INCR 1 can be any size for read or write
• INCR burst (more than one transfer) are only 32-bit or 64-bit
• No transaction is marked as FIXED
• Write transfers with all byte strobes low can occur.
8.1.3 AXI transaction IDs
The AXI ID signal is encoded as follows:
• For the data side read bus, ARIDM0, is encoded as follows:
— 2'b00 for noncacheable accesses
— 2'b01 is unused
— 2'b10 for linefill 0 accesses
— 2'b11 for linefill 1 accesses.
Write ID width None
Read ID capability 4
Read ID width 2
Table 8-2 AXI master 1 interface attributes (continued)
Attribute Format
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