ARM Cortex A9 User Manual

Introduction
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-6
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1.4 Features
The Cortex-A9 processor includes the following features:
• superscalar, variable length, out-of-order pipeline with dynamic branch prediction
• full implementation of the ARM architecture v7-A instruction set
• Security Extensions
• Harvard level 1 memory system with Memory Management Unit (MMU).
• two 64-bit AXI master interfaces with Master 0 for the data side bus and Master 1 for the
instruction side bus
• ARMv7 Debug architecture
• support for trace with the Program Trace Macrocell (PTM) interface
• support for advanced power management with up to three power domains
• optional Preload Engine
• optional Jazelle hardware acceleration
• optional data engine with MPE and VFPv3.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design