ARM Cortex A9 User Manual

Preload Engine
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 9-4
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9.3 PLE operations
The following sections describe the PLE operations:
• Preload Engine FIFO flush operation
• Preload Engine pause channel operation
• Preload Engine resume channel operation
• Preload Engine kill channel operation on page 9-5
• PLE Program New Channel operation on page 9-5.
For all Preload Engine operations:
• NSACR.PLE controls Non-secure execution.
• PLEUAR.EN controls User execution.
• the operations are only available in configurations where the Preload Engine is present,
otherwise an Undefined Instruction exception is taken.
9.3.1 Preload Engine FIFO flush operation
The PLEFF operation characteristics are:
Purpose Flushes all PLE channels programmed previously including the PLE
channel being executed.
To perform the PLE FIFO Flush operation, use:
MCR p15, 0, <Rt>, c11, c2, 1
<Rt> is not taken into account in this operation.
9.3.2 Preload Engine pause channel operation
The PLEPC operation characteristics are:
Purpose Pauses PLE activity.
You can perform a PLEPC operation even if no PLE channel is active. In this case, even if a
new PLE channel is programmed afterwards, its execution does not start until after a PLE
Resume Channel operation.
To perform the PLE PC operation, use:
MCR p15, 0, <Rt>, c11, c3, 0
<Rt> is not taken into account in this operation.
9.3.3 Preload Engine resume channel operation
The PLERC operation characteristics are:
Purpose Causes Preload Engine activity to resume.
If you perform a PLERC operation when the PLE is not paused, the Resume Channel operation
is ignored.
To perform a PLERC operation, use:
MCR p15, 0, <Rt>, c11, c3, 1

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design