ARM Cortex A9 User Manual

Preload Engine
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9.3.4 Preload Engine kill channel operation
The PLEKC operation characteristics are:
Purpose Kills the active PLE channel.
This operation does not operate on any PLE request in the PLE FIFO.
To perform a PLEKC operation, use
MCR p15, 0, <Rt>, c11, c3, 2
9.3.5 PLE Program New Channel operation
The PLE Program new channel operation characteristics are:
Purpose Programs a new memory region to preload into L2 memory.
Figure 9-1 shows the <Rt>. and <Rt2> bit assignments for PLE program new channel
operations. Rt is the register that contains the Base address. Rt2 is the register that contains the
length, stride, and number of blocks.
Figure 9-1 Program new channel operation bit assignments
Table 9-1 shows the PLE program new channel operation bit assignments.
To program a new channel operation, use the MCRR operation:
MCRR p15, 0, <Rt>,<Rt2> c11; Program new PLE channel
Length
31 18 17 10 9 2 1 0
Stride Number of blocks
RAZ/
WI
63 34 32
Base address (VA)
RAZ/
WI
33
Table 9-1 PLE program new channel operation bit assignments
Bits Name Description
[63:34] Base address (VA) This is the 32-bit Base Virtual Address of the first block of memory to preload. The address is aligned
on a word boundary. That is, bits [33:32] are RAZ/WI.
[33:32] - RAZ/WI
[31:18] Length Specifies the length of the block to preload.
Length is encoded as word multiples. The range is from 14’b0000000000, a single word block, to
14’b11111111111111, a 16K word block.
[17:10] Stride Indicates the preload stride between blocks. The preload stride is the difference between the start
address of two blocks. The stride is encoded as a word multiple. The range is from 8’b00000000,
contiguous blocks, to 8’b11111111, prefetch blocks every 256 words.
[9:2] Number of blocks Specifies the number of blocks to preload.
Values range from 8’b00000000, indicating a single block preload, to 8’b11111111 indicating 256
blocks.
[1:0] - RAZ/WI

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design