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Preload Engine

ID073015 Non-Confidential

9.2 PLE control register descriptions

The PLE control registers are CP15 registers, accessed when CRn is c11. See c11 registers on

page 4-10. The following sections describe the PLE control registers:

• PLE ID Register on page 4-36

• PLE Activity Status Register on page 4-36

• PLE FIFO Status Register on page 4-37

• Preload Engine User Accessibility Register on page 4-38

• Preload Engine Parameters Control Register on page 4-39.

For all CP15 c11 system control registers, NSAC.PLE controls Non-secure accesses. PLE

operations on page 9-4 shows the operations to use with these control registers.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design