ARM Cortex A9 - 9.2 PLE control register descriptions

Preload Engine
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9.2 PLE control register descriptions
The PLE control registers are CP15 registers, accessed when CRn is c11. See c11 registers on
page 4-10. The following sections describe the PLE control registers:
• PLE ID Register on page 4-36
• PLE Activity Status Register on page 4-36
• PLE FIFO Status Register on page 4-37
• Preload Engine User Accessibility Register on page 4-38
• Preload Engine Parameters Control Register on page 4-39.
For all CP15 c11 system control registers, NSAC.PLE controls Non-secure accesses. PLE
operations on page 9-4 shows the operations to use with these control registers.