ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-37
ID073015 Non-Confidential
Attributes See Table 4-12 on page 4-10.
Figure 4-16 shows the PLEASR bit assignments.
Figure 4-16 PLEASR bit assignments
Table 4-43 shows the PLEASR bit assignments.
To access the PLEASR, read the CP15 register with:
MRC p15, 0, <Rt>, c11, c0, 2; Read PLEASR
4.3.18 PLE FIFO Status Register
The PLEFSR characteristics are:
Purpose Indicates how many entries remain available in the PLE FIFO.
Usage constraints The PLEFSR is:
• common to Secure and Non-secure states
• accessible in User and privileged modes, regardless of any
configuration bit.
NSAC.PLE controls Non-secure accesses.
Configurations Available in all Cortex-A9 configurations regardless of whether a PLE is
present or not.
Attributes See Table 4-12 on page 4-10.
Figure 4-17 shows the PLEFSR bit assignments.
Figure 4-17 PLESFR bit assignments
31 1 0
RRAZ
Table 4-43 PLEASR bit assignments
Bits Name Function
[31:1] - Reserved, RAZ
[0] R PLE Channel running:
1 The Preload Engine is handling a PLE request.
31 450
Available
entries
RAZ/WI

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design