ARM Cortex A9 User Manual

Jazelle DBX registers
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5.2 CP14 Jazelle register summary
In the Cortex-A9 implementation of the Jazelle Extension:
• Jazelle state is supported.
•The
BXJ instruction enters Jazelle state.
Table 5-1 shows the CP14 Jazelle registers. For all Jazelle register accesses, CRm and Op2 are
zero. All Jazelle registers are 32 bits wide.
See the ARM Architecture Reference Manual for information about the Jazelle Extension.
Table 5-1 CP14 Jazelle registers summary
Op1 CRn Name Type Reset Page
7 0 Jazelle ID Register (JIDR)
RW
a
0xF4100168 page 5-4
7 1 Jazelle OS Control Register (JOSCR) RW - page 5-5
7 2 Jazelle Main Configuration Register (JMCR) RW - page 5-6
7 3 Jazelle Parameters Register RW - page 5-7
7 4 Jazelle Configurable Opcode Translation Table Register WO - page 5-8
a. See Write operation of the JIDR on page 5-5 for the effect of a write operation.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design