ARM Cortex A9 User Manual

Jazelle DBX registers
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To access the JMCR, read or write the CP14 register with:
MRC p14, 7, <Rd>, c2, c0, 0; Read JMCR
MCR p14, 7, <Rd>, c2, c0, 0; Write JMCR
5.3.4 Jazelle Parameters Register
The Jazelle Parameters Register characteristics are:
Purpose Describes the configuration parameters of the Jazelle hardware.
Usage constraints Only accessible in privileged modes.
Configurations Available in all configurations.
Attributes See the register summary in Table 5-1 on page 5-3.
Figure 5-4 shows the Jazelle Parameters Register bit assignments.
Figure 5-4 Jazelle Parameters Register bit assignments
[27] IS The Index Size (IS) bit specifies the size of the index associated with quick object field accesses:
0 Quick object field indices are 8 bits.
1 Quick object field indices are 16 bits.
[26] SP The Static Pointer (SP) bit controls how the Jazelle hardware treats static references:
0 Static references are treated as handles.
1 Static references are treated as pointers.
[25:1] - UNK/SBZP.
[0] JE The Jazelle Enable (JE) bit controls whether the Jazelle hardware is enabled, or is disabled:
0 The Jazelle hardware is disabled:
•
BXJ instructions behave like BX instructions
• setting the J bit in the CPSR generates a Jazelle-Disabled Jazelle exception.
1 The Jazelle hardware is enabled:
•
BXJ instructions enter Jazelle state
• setting the J bit in the CPSR enters Jazelle state.
Table 5-4 JMCR bit assignments (continued)
Bits Name Function
31 22 21 17 16 12 11 8 7 4 3 0
UNK/SBZP BSH sADO ARO STO ODO

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design