ARM Cortex A9 User Manual

Level 2 Memory Interface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 8-9
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8.3 STRT instructions
Take particular care with noncacheable write accesses when using the STRT instruction. To put
the correct information on the external bus ensure one of the following:
• The access is to Strongly-ordered memory.
This ensures that the
STRT instruction does not merge in the store buffer.
• The access is to Device memory.
This ensures that the
STRT instruction does not merge in the store buffer.
•A
DSB instruction is issued before and after the STRT .
This prevents an
STRT from merging into an existing slot at the same 64-bit address, or
merging with another write at the same 64-bit address.
Table 8-6 shows Cortex-A9 modes and corresponding AxPROT values.
Table 8-6 Cortex-A9 mode and AxPROT values
Processor mode Type of access Value of AxPROT
User Cacheable read access User
Privileged Privileged
User Noncacheable read access User
Privileged Privileged
- Cacheable write access Always marked as Privileged
User Noncacheable write access User
Privileged Noncacheable write access Privileged, except when using
STRT

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design