Level 2 Memory Interface
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8.2.3 Write full line of zeros
When this feature is enabled, the Cortex-A9 processor can write entire non-coherent cache lines
full of zero to the L2C-310 cache controller with a single request. This provides a performance
improvement and some power savings. This feature can optimize the performance of the
processor, but it requires a slave that is optimized for this special access. The requests are
marked as write full line of zeros by having the associated AW US E RM 0[7 ] bit set.
Setting bit [3] of the ACTLR enables this feature. See Auxiliary Control Register on page 4-27.
You must program the L2C-310 Cache Controller first, prior to enabling the feature in the
Cortex-A9 processor, to support this feature. See the CoreLink Level 2 Cache Controller
(L2C-310) Technical Reference Manual.
8.2.4 Speculative coherent requests
This optimization is available for Cortex-A9 MPCore processors only. See the Cortex-A9
MPCore TRM.
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