ARM Cortex A9 User Manual

Level 2 Memory Interface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 8-8
ID073015 Non-Confidential
8.2.3 Write full line of zeros
When this feature is enabled, the Cortex-A9 processor can write entire non-coherent cache lines
full of zero to the L2C-310 cache controller with a single request. This provides a performance
improvement and some power savings. This feature can optimize the performance of the
processor, but it requires a slave that is optimized for this special access. The requests are
marked as write full line of zeros by having the associated AW US E RM 0[7 ] bit set.
Setting bit [3] of the ACTLR enables this feature. See Auxiliary Control Register on page 4-27.
You must program the L2C-310 Cache Controller first, prior to enabling the feature in the
Cortex-A9 processor, to support this feature. See the CoreLink Level 2 Cache Controller
(L2C-310) Technical Reference Manual.
8.2.4 Speculative coherent requests
This optimization is available for Cortex-A9 MPCore processors only. See the Cortex-A9
MPCore TRM.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design