System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-27
ID073015 Non-Confidential
Attempts to read or write the SCTLR from secure or Non-secure User modes result in an
Undefined Instruction exception.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH
result in an Undefined Instruction exception.
Attempts to write secure modify only bits in non-secure privileged modes are ignored.
Attempts to read secure modify only bits return the secure bit value.
Attempts to modify RO bits are ignored.
To access the SCTRL, read or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c0, 0; Read SCTLR
MCR p15, 0,<Rd>, c1, c0, 0; Write SCTLR
4.3.10 Auxiliary Control Register
The ACTLR characteristics are:
Purpose Controls:
• parity checking, if implemented
• allocation in one way
• exclusive caching with the L2 cache
• coherency mode, Symmetric Multiprocessing (SMP) or Asymmetric
Multiprocessing (AMP)
• speculative accesses on AXI
• broadcast of cache, branch predictor, and TLB maintenance
operations
• write full line of zeros mode optimization for L2C-310 cache
requests.
Usage constraints The ACTLR is:
• Only accessible in privileged modes.
• Common to the Secure and Non-secure states.
• RW in Secure state.
• RO in Non-secure state if NSACR.NS_SMP = 0.
[2] C bit Banked Determines if data can be cached at any available cache level:
0 Data caching disabled at all levels. This is the reset value.
1 Data caching enabled.
[1] A bit Banked Enables strict alignment of data to detect alignment faults in data accesses:
0 Strict alignment fault checking disabled. This is the reset value.
1 Strict alignment fault checking enabled.
[0] M bit Banked Enables the MMU:
0 MMU disabled. This is the reset value.
1 MMU enabled.
Table 4-35 SCTLR bit assignments (continued)
Bits Name Access Function
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