System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-26
ID073015 Non-Confidential
[27] NMFI RO Non-maskable FIQ support.
The bit cannot be configured by software.
The CFGNMFI signal defines the reset value.
[26] - - RAZ/SBZP.
[25] EE bit Banked Determines how the E bit in the CPSR is set on an exception:
0 CPSR E bit is set to 0 on an exception
1 CPSR E bit is set to 1 on an exception.
This value also indicates the endianness of the translation table data for translation table lookups.
0 little-endian
1 big-endian.
The CFGEND signal defines the reset value.
[24] - - RAZ/WI.
[23:22] - - RAO/SBOP.
[21] - - RAZ/WI.
[20:19] - - RAZ/SBZP.
[18] - - RAO/SBOP.
[17] HA - RAZ/WI.
[16] - - RAO/SBOP.
[15] - - RAZ/SBZP.
[14] RR Secure
modify
only
Replacement strategy for the instruction cache, the BTAC, and the instruction and data micro TLBs.
This bit is RW in Secure state and RO in Non-secure state:
0 Random replacement. This is the reset value.
1 Round-robin replacement.
[13] V Banked Vectors bit. This bit selects the base address of the exception vectors:
0 Normal exception vectors, base address
0x00000000
.
The Security Extensions are implemented, so this base address can be remapped.
1 High exception vectors, Hivecs, base address
0xFFFF0000
.
This base address is never remapped.
At reset the value for the secure version if this bit is taken from VINITHI.
[12] I bit Banked Determines if instructions can be cached at any available cache level:
0 Instruction caching disabled at all levels. This is the reset value.
1 Instruction caching enabled.
[11] Z bit Banked Enables program flow prediction:
0 Program flow prediction disabled. This is the reset value.
1 Program flow prediction enabled.
[10] SW bit Banked SWP/SWPB enable bit:
0 SWP and SWPB are
UNDEFINED.This is the reset value.
1 SWP and SWPB perform normally.
[9:7] - - RAZ/SBZP.
[6:3] - - RAO/SBOP.
Table 4-35 SCTLR bit assignments (continued)
Bits Name Access Function
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