ARM Cortex A9 User Manual

Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-4
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2.2 Interfaces
The processor has the following external interfaces:
• AXI interface
• APB external debug interface
• Program Flow Trace and Program Trace Macrocell.
2.2.1 AXI interface
The Cortex-A9 processor implements AMBA 3 AXI interface. See the AMBA AXI Protocol
Specification for more information.
2.2.2 APB external debug interface
The Cortex-A9 processor implements the ARM Debug interface version 5. See the CoreSight
Architecture Specification for more information.
2.2.3 Program Flow Trace and Program Trace Macrocell
The Cortex-A9 processor implements the Program Flow Trace (PFT) architecture protocol. See
the CoreSight Program Flow Trace Architecture Specification.
PFT is an instruction-only trace protocol that uses waypoints to correlate the trace to the code
image. Waypoints are changes in the program flow or events such as branches or changes in
context ID that must be output to enable the trace. See the CoreSight PTM-A9 Technical
Reference Manual for more information about tracing with waypoints.
Program Trace Macrocell (PTM) is a macrocell that implements the PFT architecture.
Figure 2-2 shows the PTM interface signals.
Figure 2-2 PTM interface signals
See Appendix A Signal Descriptions and the CoreSight PTM-A9 Technical Reference Manual
for more information.
Trace must be disabled in some regions. The prohibited regions are described in the ARM
Architecture Reference Manual. The Cortex-A9 processor must determine prohibited regions
for non-invasive debug in regions, including trace, performance monitoring, and PC sampling.
No waypoints are generated for instructions that are within a prohibited region.
Cortex-A9 processor
WPTCOMMIT[1:0]WPTENABLE
WPTCONTEXTID[31:0]
WPTEXCEPTIONTYPE[3:0]
WPTFLUSH
WPTLINK
WPTPC[31:0]
WPTT32LINK
WPTTAKEN
WPTTARGETJBIT
WPTTARGETPC[31:0]
WPTTARGETTBIT
WPTTRACEPROHIBITED
WPTTYPE[2:0]
WPTVALID
WPTnSECURE
WPTFIFOEMPTY

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design