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ID073015 Non-Confidential

Appendix A

Signal Descriptions

This appendix describes the Cortex-A9 signals. It contains the following sections:

• Clock signals on page A-2

• Reset signals on page A-3

• Interrupts on page A-4

• Configuration signals on page A-5

• WFE and WFI standby signals on page A-6

• Power management signals on page A-7

• AXI interfaces on page A-8

• Performance monitoring signals on page A-14

• Exception flags signal on page A-17

• Parity signal on page A-18

• MBIST interface on page A-19

• Scan test signal on page A-20

• External Debug interface on page A-21

• PTM interface signals on page A-24.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design