To Next Page

To Previous Page

Debug

ID073015 Non-Confidential

10.6 Debug management registers

The Debug management registers define the standardized set of registers that is implemented by

all CoreSight components. This section describes these registers.

You can access these registers:

• through the internal CP14 interface

• through the APB using the relevant offset when PADDRDBG[12]=0

See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for additional

information about these registers.

Table 10-9 shows the contents of the management registers for the Cortex-A9 debug unit.

10.6.1 Peripheral Identification Registers

The Peripheral Identification Registers are read-only registers that provide standard information

required by all components that conform to the ARM Debug interface v5 specification. The

Peripheral Identification Registers are accessible from the Debug APB bus. Only bits [7:0] of

each register are used. The remaining bits are Read-As-Zero. The values in these registers are

fixed.

Table 10-9 Debug management registers

number

Offset Name CRn Op1 CRm OP2 Type Description

960

0xF00

DBGITCTRL c7 0 c0 4 RAZ/

Integration Mode Control Register

961-999

0xF04-

0xF9C

-RAZReserved

1000

0xFA0

DBGCLAIMSET c7 0 c8 6 RW Claim Tag Set Register

1001

0xFA4

DBGCLAIMCLR c7 0 c9 6 RW Claim Tag Clear Register

1002-

1003

0xFA8-

0xFBC

-RAZReserved

1004

0xFB0

DBGLAR c7 0 c12 6 WO Lock Access Register

1005

0xFB4

DBGLSR c7 0 c13 6 RO Lock Status Register

1006

0xFB8

DBGAUTHSTATUS c7 0 c14 6 RO Authentication Status Register

1007-

1009

0xFBC-

0xFC4

-RAZReserved

1010

0xFC8

DBGDEVID c7 0 c2 7 RAZ/

Debug Device ID Register

1011

0xFCC

DBGDEVTYPE c7 0 c3 7 RO Device Type Register

1012-

1023

0xFD0-

0xFEC

DBGPID c7 0 c4-c8 7 RO See Peripheral Identification

Registers.

1020-

1023

0xFF0-

0xFFC

DBGCID c7 0 c12-c15 7 RO See Component Identification

Registers on page 10-14

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex A9 and is the answer not in the manual?

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design