ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-14
ID073015 Non-Confidential
Table 10-10 shows the register number, offset, name, type, value and description that are
associated with each Peripheral Identification Register.
See the ARM Debug Interface v5 Specification for more information on the Peripheral ID
Registers.
10.6.2 Component Identification Registers
The Component Identification Registers are read-only registers that provide standard
information required by all components that conform to the ARM Debug interface v5
specification. The Component Identification Registers are accessible from the Debug APB bus.
Only bits [7:0] of each register are used the remaining bits Read-As-Zero. The values in these
registers are fixed.
Table 10-11 shows the register number, offset, name, type, value and description that are
associated with each Component Identification Register.
See the ARM Debug Interface v5 Specification for more information on the Peripheral ID
Registers.
Table 10-10 Peripheral Identification Register Summary
Register
number
Offset Name Type Value Description
1012
0xFD0 DBGPID4 RO 0x04 Peripheral Identification Register 4
1013
0xFD4 DBGPID5 RO - Reserved
1014
0xFD8 DBGPID6 RO - Reserved
1015
0xFDC DBGPID7 RO - Reserved
1016
0xFE0 DBGPID0 RO 0x09 Peripheral Identification Register 0
1017
0xFE4 DBGPID1 RO 0xBC Peripheral Identification Register 1
1018
0xFE8 DBGPID2 RO 0x0B Peripheral Identification Register 2
1019
0xFEC DBGPID3 RO 0x00 Peripheral Identification Register 3
Table 10-11 Component Identification Register Summary
Register
number
Offset Name Type Value Description
1020
0xFF0 DBGCID0 RO 0x0D Component Identification Register 0
1021
0xFF4 DBGCID1 RO 0x90 Component Identification Register 1
1022
0xFF8 DBGCID2 RO 0x05 Component Identification Register 2
1023
0xFFC DBGCID3 RO 0xB1 Component Identification Register 3

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design