ARM Cortex A9 User Manual

Performance Monitoring Unit
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11.2 PMU register summary
You can access the PMU counters, and their associated control registers:
• through the internal CP15 interface
• through the APB, using the relevant offset when PADDRDBG[12]=1.
Table 11-1 gives a summary of the Cortex-A9 PMU registers.
Table 11-1 PMU register summary
Register
number
Offset CRn Op1 CRm Op2 Name Type Description
0
0x000 c9 0 c13 2 PMXEVCNTR0 RW Event Count Register, see the ARM
Architecture Reference Manual
1
0x004 c90c132PMXEVCNTR1RW
2
0x008 c90c132PMXEVCNTR2RW
3
0x00C c90c132PMXEVCNTR3RW
4
0x010 c90c132PMXEVCNTR4RW
5
0x014 c90c132PMXEVCNTR5RW
6-30
0x018-
0x078
--- -- - Reserved
31
0x07C c9 0 c13 0 PMCCNTR RW Cycle Count Register, see the ARM
Architecture Reference Manual
32-255
0x080-
0x3FC
--- -- - Reserved
256
0x400 c9 0 c13 1 PMXEVTYPER0 RW Event Type Selection Register, see the ARM
Architecture Reference Manual
257
0x404 c90c131PMXEVTYPER1RW
258
0x408 c90c131PMXEVTYPER2RW
259
0x40C c90c131PMXEVTYPER3RW
260
0x410 c90c131PMXEVTYPER4RW
261
0x414 c90c131PMXEVTYPER5RW
262-767
0x418-
0xBFC
--- -- - Reserved
768
0xC00 c9 0 c12 1 PMCNTENSET RW Count Enable Set Register, see the ARM
Architecture Reference Manual
769-775
0xC04-
0xC1C
--- -- - Reserved
776
0xC20 c9 0 c12 2 PMCNTENCLR RW Count Enable Clear Register, see the ARM
Architecture Reference Manual
777-783
0xC24-
0xC3C
--- -- - Reserved
784
0xC40 c9 0 c14 1 PMINTENSET RW Interrupt Enable Set Register, see the ARM
Architecture Reference Manual

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design