ARM Cortex A9 User Manual

Performance Monitoring Unit
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-4
ID073015 Non-Confidential
785-791 0xC44-
0xC5C
--- -- - Reserved
792
0xC60 c9 0 c14 2 PMINTENCLR RW Interrupt Enable Clear Register, see the ARM
Architecture Reference Manual
793-799
0xC64-
0xC7C
--- -- - Reserved
800
0xC80 c9 0 c12 3 PMOVSR RW Overflow Flag Status Register, see the ARM
Architecture Reference Manual
801-807
0xC84-
0xC7C
--- -- - Reserved
808
0xCA0 c9 0 c12 4 PMSWINC WO Software Increment Register, see the ARM
Architecture Reference Manual
809-831
0xCA4-
0xCFC
--- -- - Reserved
832-895 - - - - - - - -
896
0xE00 --- -- - Reserved
897
0xE04 c9 0 c12 0 PMCR RW Performance Monitor Control Register, see
the ARM Architecture Reference Manual
898
0xE08 c90c140PMUSERENR
RW
a
User Enable Register, see the ARM
Architecture Reference Manual
- c9 0 c12 5 PMSELR RW Event Counter Select Register, see the ARM
Architecture Reference Manual
899-959
0xE0C -
0xEFC
--- -- - Reserved
960-1023
0xF00 -
0xFFC
--- -PMU
Management
Registers
- PMU management registers on page 11-5
a. Read-only in User mode.
Table 11-1 PMU register summary (continued)
Register
number
Offset CRn Op1 CRm Op2 Name Type Description

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design