ARM Cortex A9 - A.2 Reset signals

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-3
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A.2 Reset signals
Table A-2 shows the reset and reset control signals.
See Reset on page 2-6.
Table A-2 Reset signals
Name I/O Source Description
nCPURESET I Reset controller Cortex-A9 processor reset.
nDBGRESET I Cortex-A9 processor debug logic reset.
NEONCLKOFF
a
a. Only if the MPE is present.
I MPE SIMD logic clock control:
0 Do not cut MPE SIMD logic clock.
1 Cut MPE SIMD logic clock.
nNEONRESET
a
I Cortex-A9 MPE SIMD logic reset.