ARM Cortex A9 User Manual

Signal Descriptions
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A.2 Reset signals
Table A-2 shows the reset and reset control signals.
See Reset on page 2-6.
Table A-2 Reset signals
Name I/O Source Description
nCPURESET I Reset controller Cortex-A9 processor reset.
nDBGRESET I Cortex-A9 processor debug logic reset.
NEONCLKOFF
a
a. Only if the MPE is present.
I MPE SIMD logic clock control:
0 Do not cut MPE SIMD logic clock.
1 Cut MPE SIMD logic clock.
nNEONRESET
a
I Cortex-A9 MPE SIMD logic reset.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design