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Signal Descriptions

ID073015 Non-Confidential

A.4 Configuration signals

Table A-4 shows the configuration signals only sampled during reset of the processor.

Table A-5 shows the CP15SDISABLE signal.

Table A-4 Configuration signals

Name I/O Source Description

CFGEND I System configuration control Controls the state of EE bit in the SCTLR at reset:

0 EE bit is LOW.

1 EE bit is HIGH.

CFGNMFI I Configures fast interrupts to be non-maskable:

0 Clear the NMFI bit in the CP15 c1 Control Register.

1 Set the NMFI bit in the CP15 c1 Control Register.

TEINIT I Default exception handling state:

0 ARM.

1 Thumb.

This signal sets the SCTLR.TE bit at reset.

VINITHI I Controls the location of the exception vectors at reset:

0 Start exception vectors at address

0x00000000.

1 Start exception vectors at address

0xFFFF0000

This signal sets the SCTLR.V bit.

Table A-5 CP15SDISABLE signal

Name I/O Source Description

CP15SDISABLE I Security

controller

Disables write access to some system control processor registers in Secure state:

0 Not enabled.

1 Enabled.

See System Control Register on page 4-25.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design