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Memory Management Unit

ID073015 Non-Confidential

Domains

The Cortex-A9 processor supports 16 access domains.

TLB

The Cortex-A9 processor implements a 2-level TLB structure. Four entries in the main TLB are

lockable.

ASIDs

Main TLB entries can be global, or can be associated with particular processes or applications

using Address Space Identifiers (ASIDs). ASIDs enable TLB entries to remain resident during

context switches, avoiding the requirement of reloading them subsequently. See Invalidate TLB

Entries on ASID Match on page 4-45.

System control coprocessor

TLB maintenance and configuration operations are controlled through a dedicated coprocessor,

CP15, integrated within the processor. This coprocessor provides a standard mechanism for

configuring the level one memory system.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design