Memory Management Unit
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 6-3
ID073015 Non-Confidential
Domains
The Cortex-A9 processor supports 16 access domains.
TLB
The Cortex-A9 processor implements a 2-level TLB structure. Four entries in the main TLB are
lockable.
ASIDs
Main TLB entries can be global, or can be associated with particular processes or applications
using Address Space Identifiers (ASIDs). ASIDs enable TLB entries to remain resident during
context switches, avoiding the requirement of reloading them subsequently. See Invalidate TLB
Entries on ASID Match on page 4-45.
System control coprocessor
TLB maintenance and configuration operations are controlled through a dedicated coprocessor,
CP15, integrated within the processor. This coprocessor provides a standard mechanism for
configuring the level one memory system.
To Next Page
Loading...
