ARM Cortex A9 User Manual

Performance Monitoring Unit
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-5
ID073015 Non-Confidential
11.3 PMU management registers
The PMU management registers define the standardized set of registers that is implemented by
all CoreSight components. This section describes these registers.
You can access these registers through the APB interface only, using the offset listed in
Table 11-2 when PADDRDBG[12]=1.
Table 11-2 shows the contents of the management registers for the Cortex-A9 PMU.
11.3.1 Peripheral Identification Registers
The Peripheral Identification Registers are read-only registers that provide standard information
required by all components that conform to the ARM Debug interface v5 specification. The
Peripheral Identification Registers are accessible from the Debug APB bus. Only bits [7:0] of
each register are used the remaining bits Read-As-Zero. The values in these registers are fixed.
Table 11-3 shows the register number, offset value, name, type, value, and description that are
associated with each PMU Peripheral Identification Register.
Table 11-2 PMU management registers
Register
number
Offset Name Type Description
960
0xF00 PMITCTRL RAZ/WI Integration Mode Control Register
961-999
0xF04-0xF9C -RAZReserved
1000
0xFA0 PMCLAIMSET RW Claim Tag Set Register
1001
0xFA4 PMCLAIMCLR RW Claim Tag Clear Register
1002-1003
0xFA8-0xFBC -RAZReserved
1004
0xFB0 PMLAR WO Lock Access Register
1005
0xFB4 PMLSR RO Lock Status Register
1006
0xFB8 PMAUTHSTATUS RO Authentication Status Register
1007-1009
0xFBC-0xFC4 -RAZReserved
1010
0xFC8 PMDEVID RAZ/WI Device ID Register
1011
0xFCC PMDEVTYPE RO Device Type Register
1012-1019
0xFD0-0xFEC PMPID RO See Peripheral Identification Registers
1020- 1023
0xFF0-0xFFC PMCID RO See Component Identification Registers on page 11-6
Table 11-3 Peripheral Identification Registers
Register
number
Offset Name Type Value Description
1012
0xFD0 PMPID4 RO 0x04 Peripheral Identification Register 4
1013
0xFD4 PMPID5 RO - Reserved
1014
0xFD8 PMPID6 RO - Reserved
1015
0xFDC PMPID7 RO - Reserved

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design