ARM Cortex A9 User Manual

Performance Monitoring Unit
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-6
ID073015 Non-Confidential
See the ARM Debug Interface v5 Specification for more information on the Peripheral ID
Registers.
11.3.2 Component Identification Registers
The Component Identification Registers are read-only registers that provide standard
information required by all components that conform to the ARM Debug interface v5
specification. The Component Identification Registers are accessible from the Debug APB bus.
Only bits [7:0] of each register are used the remaining bits Read-As-Zero. The values in these
registers are fixed.
Table 11-4 shows the offset value, register number, and value that are associated with each PMU
Component Identification Register.
See the ARM Debug Interface v5 Specification for more information on the Component ID
Registers.
1016 0xFE0 PMPID0 RO 0xA0 Peripheral Identification Register 0
1017
0xFE4 PMPID1 RO 0xB9 Peripheral Identification Register 1
1018
0xFE8 PMPID2 RO 0x0B Peripheral Identification Register 2
1019
0xFEC PMPID3 RO 0x00 Peripheral Identification Register 3
Table 11-3 Peripheral Identification Registers (continued)
Register
number
Offset Name Type Value Description
Table 11-4 Component Identification Registers
Register
number
Offset Name Type Value Description
1020
0xFF0 PMCID0 RO 0x0D Component Identification Register 0
1021
0xFF4 PMCID1 RO 0x90 Component Identification Register 1
1022
0xFF8 PMCID2 RO 0x05 Component Identification Register 2
1023
0xFFC PMCID3 RO 0xB1 Component Identification Register 3

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design