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Programmers Model

ID073015 Non-Confidential

3.8 Memory model

The Cortex-A9 processor views memory as a linear collection of bytes numbered in ascending

order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second

stored word. The processor can store words in memory in either big-endian format or

little-endian format.

Instructions are always treated as little-endian.

Note

ARMv7 does not support the BE-32 memory model.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design