ARM Cortex A9 User Manual

Programmers Model
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3.7 Modes of operation and execution
This section describes the instruction set states and modes of the Cortex-A9 processor in:
• Operating states.
3.7.1 Operating states
The processor has the following instruction set states controlled by the T bit and J bit in the
CPSR.
ARM state The processor executes 32-bit, word-aligned ARM instructions.
Thumb state The processor executes 16-bit and 32-bit, halfword-aligned Thumb
instructions.
Jazelle state The processor executes variable length, byte-aligned Jazelle instructions.
ThumbEE state The processor executes a variant of the Thumb instruction set designed as
a target for dynamically generated code. This is code compiled on the
device either shortly before or during execution from a portable bytecode
or other intermediate or native representation.
The J bit and the T bit determine the instruction set used by the processor. Table 3-1 shows the
encoding of these bits.
Note
Transition between ARM and Thumb states does not affect the processor mode or the register
contents. See the ARM Architecture Reference Manual for information on entering and exiting
ThumbEE state.
Table 3-1 CPSR J and T bit encoding
J T Instruction set state
00 ARM
0 1 Thumb
1 0 Jazelle
1 1 ThumbEE

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design