ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-4
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10.3 Debug register features
This section introduces the debug register features in:
• Processor interfaces
• Breakpoints and watchpoints
• Effects of resets on debug registers.
10.3.1 Processor interfaces
The Cortex-A9 processor has the following interfaces to the debug and performance monitor:
Debug registers
This interface is Baseline CP14, Extended CP14, and memory-mapped.
See CTI signals on page A-22 and APB interface signals on page A-22.
Performance monitor
This interface is CP15 based and memory-mapped. See Performance monitoring
on page 2-3 and Chapter 11 Performance Monitoring Unit.
10.3.2 Breakpoints and watchpoints
The processor supports six breakpoints, two with Context ID comparison, BRP4 and BRP5 and
four watchpoints.
See Breakpoint Value Registers bit functions on page 10-7 and BCR Register bit assignments on
page 10-8 for more information on breakpoints.
See Watchpoint Value Registers bit functions on page 10-11, WCR Register bit assignments on
page 10-11 and Watchpoints on page 10-15 for more information on watchpoints.
10.3.3 Effects of resets on debug registers
nDBGRESET
This is the debug logic reset signals. This signal must be asserted during a
power-on reset sequence. Other reset signals, nCPURESET and
nNEONRESET, if MPE is present, have no effect on the debug logic.
On a debug reset:
• The debug state is unchanged. That is, DBGSCR.HALTED is unchanged.
• The processor removes the pending halting debug events DBGDRCR.HaltReq.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design