ARM Cortex A9 User Manual

ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-1
ID073015 Non-Confidential
Chapter 11
Performance Monitoring Unit
This chapter describes the Performance Monitoring Unit (PMU) and the registers that it uses. It
contains the following sections:
• About the Performance Monitoring Unit on page 11-2
• PMU register summary on page 11-3
• PMU management registers on page 11-5
• Performance monitoring events on page 11-7.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design