EasyManua.ls Logo

ARM Cortex A9 - 2.4 Power management

ARM Cortex A9
213 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-10
ID073015 Non-Confidential
2.4 Power management
The processor provides mechanisms to control both dynamic and static power dissipation. Static
power control is implementation-specific. This section describes:
Energy efficiency features
Cortex-A9 processor power control.
Power domains on page 2-13.
Cortex-A9 voltage domains on page 2-13.
2.4.1 Energy efficiency features
The features of the Cortex-A9 processor that improve energy efficiency include:
accurate branch and return prediction, reducing the number of incorrect instruction fetch
and decode operations
the use of physically addressed caches, reducing the number of cache flushes and refills,
saving energy in the system
the use of micro TLBs reduces the power consumed in translation and protection lookups
for each cycle
caches that use sequential access information to reduce the number of accesses to the tag
RAMs and to unnecessary accesses to data RAMs
instruction loops that are smaller than 64 bytes often complete without additional
instruction cache accesses, so lowering power consumption.
2.4.2 Cortex-A9 processor power control
Place holders for level-shifters and clamps are inserted around the Cortex-A9 processor to ease
the implementation of different power domains.
The Cortex-A9 processor can have the following power domains:
a power domain for Cortex-A9 processor logic
a power domain for Cortex-A9 processor MPE
a power domain for Cortex-A9 processor RAMs.
Table 2-2 shows the power modes.
Table 2-2 Cortex-A9 processor power modes
Mode
Cortex-A9
processor
RAM arrays
Cortex-A9
processor
logic
Cortex-A9
data engine
Description
Full Run Mode Powered-up Powered-up Powered-up -
Clocked Clocked
Run Mode with
MPE disabled
Powered-up Powered-up Powered-up See Coprocessor Access Control Register on
page 4-29 for information about disabling the MPE
Clocked No clock
Run Mode with
MPE powered off
Powered-up Powered-up Powered off The MPE can be implemented in a separate power
domain and be powered off separately
Clocked

Table of Contents

Related product manuals