ARM Cortex A9 User Manual

Functional Description
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Gated blocks
The Cortex-A9 processor or each processor in a CortexA9 MPCore design supports dynamic
high level clock gating of:
• the integer core
• the system control block.
• the data engine, if implemented.
Power Control Register
The Power Control Register controls dynamic high level clock gating. This register contains
fields that are common to these blocks:
• the enable bit for clock gating
• the max_clk_latency bits.
See Power Control Register on page 4-41.
Dynamic high level clock gating activity
When dynamic high level clock gating is enabled the clock of the integer core is cut in the
following cases:
• the integer core is empty and there is an instruction miss causing a linefill
• the integer core is empty and there is an instruction TLB miss
• the integer core is full and there is a data miss causing a linefill
• the integer core is full and data stores are stalled because the linefill buffers are busy.
When dynamic clock gating is enabled, the clock of the system control block is cut in the
following cases:
• there are no system control coprocessor instructions being executed
• there are no system control coprocessor instructions present in the pipeline
• performance events are not enabled
• debug is not enabled.
When dynamic clock gating is enabled, the clock of the data engine is cut when there is no data
engine instruction in the data engine and no data engine instruction in the pipeline.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design