ARM Cortex A9 User Manual

Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-8
ID073015 Non-Confidential
Processor reset
A processor or warm reset initializes the majority of the Cortex-A9 processor, apart from its
debug logic. Breakpoints and watchpoints are retained during a processor reset. Processor reset
is typically used for resetting a system that has been operating for some time. Use
nCPURESET and nNEONRESET for a warm reset.
MPE SIMD logic reset
This reset initializes all the SIMD logic of the MPE. It is expected to be applied when the SIMD
part of the MPE exits from powerdown state. This reset only applies to configurations where the
SIMD MPE logic is implemented in its own dedicated power domain, separated from the rest
of the processor logic.
ARM recommends the following reset sequence for an MPE SIMD reset:
1. Apply nNEONRESET.
2. Wait for at least nine CLK cycles. There is no harm in applying more clock cycles than
this, and maximum redundancy can be achieved by for example applying 15 cycles on
every clock domain.
3. Assert NEONCLKOFF with a value of 1’b1.
4. Wait for the equivalent of approximately 10 cycles, depending on your implementation.
This compensates for clock and reset tree latencies.
5. Release nNEONRESET.
6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock
and reset tree latencies.
7. Deassert NEONCLKOFF. This ensures that all registers in the SIMD MPE part of the
processor see the same CLK edge on exit from the reset sequence.
Use nNEONRESET to control the SIMD part of the MPE logic independently of the
Cortex-A9 processor reset. Use this reset to hold the SIMD part of the MPE in a reset state so
that the power to the SIMD part of the MPE can be safely switched on or off. See Table 2-2 on
page 2-10.
Debug reset
This reset initializes the debug logic in the Cortex-A9 uniprocessor, including breakpoints and
watchpoints values.
To perform a debug reset, you must assert the nDBGRESET signal LOW during a few CLK
cycles.
2.3.3 Dynamic high level clock gating
The following sections describe dynamic high level clock gating:
• Gated blocks on page 2-9
• Power Control Register on page 2-9
• Dynamic high level clock gating activity on page 2-9.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design